Sun SPARC(R) Enterprise Mx000 (OPL) Servers: Processor numbering and decoding CPU location.

Asset ID:	1-71-1005329.1
Update Date:	2010-08-10
Keywords:

Solution Type Technical Instruction Sure

Solution 1005329.1 : Sun SPARC(R) Enterprise Mx000 (OPL) Servers: Processor numbering and decoding CPU location.

Applies to:

Sun SPARC Enterprise M3000 Server
Sun SPARC Enterprise M4000 Server
Sun SPARC Enterprise M5000 Server
Sun SPARC Enterprise M8000 Server
Sun SPARC Enterprise M9000-32 Server - Version: Not Applicable to Not Applicable [Release: NA to NA]
All Platforms

Goal

Solaris[TM] device paths and messaging reference the ID of a given processor (in /var/adm/messages, console logs, core files, OBP probing, etc.).

This document provides the cpuid cheat sheets for the Sun SPARC Enterprise[R] Mx000 (OPL) Servers.

On the Sun SPARC Enterprise M3000, there is only one domain and only one LSB (00).

The processor numbering is based on the Logical System Board mapping therefore, the numbering is common to the Mid-Range Servers (M4000 + M5000) and High-End Servers (M8000 + M9000).
This document explains how to correctly decode an ID (cpuid and portid) to the physical location within this platform.

By correctly mapping this ID to a physical location, we know that we are servicing the right component to resolve a hardware problem. An incorrect mapping could result in replacing and/or servicing the wrong component and could cause further outages or problems on the platform.

Solution

Reminder:

- SPARC64 VI chip has two physical cores and each core has two strands (or virtual CPUs).
- SPARC64 VII chip has four physical cores and each core has two strands (or virtual CPUs).

SPARC64 VI[I] chips are either mounted :
* on the MBU for Mid-Range Servers (M3000, M4000 & M5000),
* on a CMU for High-End Servers (M8000 + M9000).

- PSB : a PSB (Physical System Board) consists of up to 4 CPUs, up to 32 DIMMs and one IOU (optional).

- XSB : In the eXtended System Board, the PSB can be either one complete unit (Uni-XSB) or divided into four subunits (Quad-XSB).

- LSB : A logical unit name of an XSB to which a logical number (LSB number) is assigned. LSB is used together with an LSB number when domains are constructed and it is referred to by the Solaris OS.

Decoding the IDs :

OpenBoot device tree :

The processor is represented as three level node structure in OpenBoot device tree (N = portid).
For SPARC64 VI, this can be represented as following :

cmp(/cmp@N)
|
---------------------------------------------------------- 
|                                                        |
|                                                        |
core (/cmp@N/core@0)                                     core (/cmp@N/core@1)
|                                                        |
-----------------------------                            -----------------------------
|                           |                            |                           |
|                           |                            |                           |
cpu (/cmp@N/core@0/cpu@0)   cpu (/cmp@N/core@0/cpu@1)    cpu (/cmp@N/core@1/cpu@0)   cpu (/cmp@N/core@1/cpu@1)

SPARC64 VII has 4 cores.

The portid is defined as :

[10]  = 1
[9]   = LSB_ID[4] = 0
[8:5] = LSB_ID[3:0]
[4:3] = Chip_ID
[2:0] = 0

10	9	8 7 6 5	4 3	2 1 0
1	0	LSB_ID	CHIP_ID	0 0 0

LSB ID : Logical System Board on which this SPARC64 VI[I] chip is mounted (0-15 for OPL)
CHIP ID : SPARC64 VI[I] chip number on specified LSB (0-3)

Note that the representation in OBP is always Hex-numbers.

Example while browsing the OpenBoot device tree of a M9000 domain composed of 3 XSBs (SPARC64 VI) :

{11} ok show-devs
[...]
/cmp@458,0/core@1
/cmp@458,0/core@0
/cmp@458,0/core@1/cpu@1
/cmp@458,0/core@1/cpu@0
/cmp@458,0/core@0/cpu@1
/cmp@458,0/core@0/cpu@0
/cmp@450,0/core@1
/cmp@450,0/core@0
/cmp@450,0/core@1/cpu@1
/cmp@450,0/core@1/cpu@0
/cmp@450,0/core@0/cpu@1
/cmp@450,0/core@0/cpu@0
/cmp@448,0/core@1
/cmp@448,0/core@0
/cmp@448,0/core@1/cpu@1
/cmp@448,0/core@1/cpu@0
/cmp@448,0/core@0/cpu@1
/cmp@448,0/core@0/cpu@0
/cmp@440,0/core@1
/cmp@440,0/core@0
/cmp@440,0/core@1/cpu@1
/cmp@440,0/core@1/cpu@0
/cmp@440,0/core@0/cpu@1
/cmp@440,0/core@0/cpu@0
/cmp@438,0/core@1
/cmp@438,0/core@0
/cmp@438,0/core@1/cpu@1
/cmp@438,0/core@1/cpu@0
/cmp@438,0/core@0/cpu@1
/cmp@438,0/core@0/cpu@0
/cmp@430,0/core@1
/cmp@430,0/core@0
/cmp@430,0/core@1/cpu@1
/cmp@430,0/core@1/cpu@0
/cmp@430,0/core@0/cpu@1
/cmp@430,0/core@0/cpu@0
/cmp@428,0/core@1
/cmp@428,0/core@0
/cmp@428,0/core@1/cpu@1
/cmp@428,0/core@1/cpu@0
/cmp@428,0/core@0/cpu@1
/cmp@428,0/core@0/cpu@0
/cmp@420,0/core@1
/cmp@420,0/core@0
/cmp@420,0/core@1/cpu@1
/cmp@420,0/core@1/cpu@0
/cmp@420,0/core@0/cpu@1
/cmp@420,0/core@0/cpu@0
/cmp@418,0/core@1
/cmp@418,0/core@0
/cmp@418,0/core@1/cpu@1
/cmp@418,0/core@1/cpu@0
/cmp@418,0/core@0/cpu@1
/cmp@418,0/core@0/cpu@0
/cmp@410,0/core@1
/cmp@410,0/core@0
/cmp@410,0/core@1/cpu@1
/cmp@410,0/core@1/cpu@0
/cmp@410,0/core@0/cpu@1
/cmp@410,0/core@0/cpu@0
/cmp@408,0/core@1
/cmp@408,0/core@0
/cmp@408,0/core@1/cpu@1
/cmp@408,0/core@1/cpu@0
/cmp@408,0/core@0/cpu@1
/cmp@408,0/core@0/cpu@0
/cmp@400,0/core@1
/cmp@400,0/core@0
/cmp@400,0/core@1/cpu@1
/cmp@400,0/core@1/cpu@0
/cmp@400,0/core@0/cpu@1
/cmp@400,0/core@0/cpu@0
[...]

To decode the logical location for /cmp@450,0/core@1/cpu@0, we need to decode the portid :

{2} ok cd /cmp@450,0/core@1/cpu@0
{2} ok .properties
status                   okay
device_type              cpu
name                     cpu
cpuid                    00000052
reg                      00000000

x450 ==> 10001010000

10	9	8 7 6 5	4 3	2 1 0
1	0	0 0 1 0	1 0	0 0 0

hence, in this case,

LSB_ID = 02
CHIP_ID = 2

/cmp@450,0/core@1/cpu@0 ==> ( LSB_ID 02 / CHIP_ID 2 ) / core@1 / cpu@0

For SPARC64 VII, there is no difference when calculating the portid, only the core ID will change.
Example :

{e} ok show-devs
[...]
/cmp@418,0/core@3
/cmp@418,0/core@2
/cmp@418,0/core@1
/cmp@418,0/core@0
/cmp@418,0/core@3/cpu@1
/cmp@418,0/core@3/cpu@0
/cmp@418,0/core@2/cpu@1
/cmp@418,0/core@2/cpu@0
/cmp@418,0/core@1/cpu@1
/cmp@418,0/core@1/cpu@0
/cmp@418,0/core@0/cpu@1
/cmp@418,0/core@0/cpu@0
[...]

{e} ok cd /cmp@418,0/core@3/cpu@1
{e} ok .properties
status                   okay
device_type              cpu
name                     cpu
cpuid                    0000001f
reg                      00000001

x418 ==> 10000011000

10	9	8 7 6 5	4 3	2 1 0
1	0	0 0 0 0	1 1	0 0 0

hence, in this case,

LSB_ID = 0
CHIP_ID = 3

/cmp@418,0/core@3/cpu@1 ==> ( LSB_ID 00 / CHIP_ID 3 ) / core@3 / cpu@0

Solaris :

Solaris[TM] device paths and messaging reference the ID of a given processor, generally in a Decimal representation, via the cpuid (prtdiag, psrinfo, /var/adm/messages, panic string ...):

The cpuid is defined as :

[9]   = LSB_ID[4] = 0
[8:5] = LSB_ID[3:0]
[4:3] = Chip_ID
[1:2] = Core_ID
[0]   = Strand_ID

9	8 7 6 5	4 3	2 1	0
0	LSB_ID	Chip_ID	Core_ID	Strand_ID

For SPARC64 VI :
. the Core_ID is either 0 or 1.
. the Strand_ID is either 0 or 1.

For SPARC64 VII :
. the Core_ID is 0, 1, 2 or 3.
. the Strand_ID is either 0 or 1.

From the previous example from a M9000 system (SPARC64 VI), the cpuid used by Solaris associated with /cmp@450,0/core@1/cpu@0 is x52 :

{2} ok cd /cmp@450,0/core@1/cpu@0
{2} ok .properties
status                   okay
device_type              cpu
name                     cpu
cpuid                    00000052
reg                      00000000

To decode the cpuid :

x52 ==> 0001010010

9	8 7 6 5	4 3	2 1	0
0	0 0 1 0	1 0	0 1	0

LSB_ID    = 02
Chip_ID   = 2
Core_ID   = 1
Strand_ID = 0

x52(82) => LSB_ID 02 / CHIP_ID 2 / core@1 / cpu@0

This can be confirmed from a prtdiag from the domain :

==================================== CPUs ====================================

   CPU              CPU            Run       L2$       CPU      CPU
LSB    Chip              ID            MHz        MB       Impl.    Mask
---    ----      --------------------  ----      ---       -----    ----
00      0          0,   1,   2,   3   2280      5.0          6      146
00      1          8,   9,  10,  11   2280      5.0          6      146
00      2         16,  17,  18,  19   2280      5.0          6      146
00      3         24,  25,  26,  27   2280      5.0          6      146
01      0         32,  33,  34,  35   2280      5.0          6      146
01      1         40,  41,  42,  43   2280      5.0          6      146
01      2         48,  49,  50,  51   2280      5.0          6      146
01      3         56,  57,  58,  59   2280      5.0          6      146
02      0         64,  65,  66,  67   2280      5.0          6      146
02      1         72,  73,  74,  75   2280      5.0          6      146
02      2         80,  81,  82,  83   2280      5.0          6      146
02      3         88,  89,  90,  91   2280      5.0          6      146

Note that the representation in Solaris is always Dec-numbers.

# psrinfo
[...]
75      on-line   since 02/14/2007 16:09:08
80      on-line   since 02/14/2007 16:09:08
81      on-line   since 02/14/2007 16:09:08
82      on-line   since 02/14/2007 16:09:08
83      on-line   since 02/14/2007 16:09:08
88      on-line   since 02/14/2007 16:09:08
[...]

# psrinfo -vp
[...]
The physical processor has 4 virtual processors (80-83)
SPARC64-VI (portid 1024 impl 0x6 ver 0x92 clock 2280 MHz)
[...]

A similar reasoning is applicable to SPARC64-VII.

{e} ok cd /cmp@418,0/core@3/cpu@1
{e} ok .properties
status                   okay
device_type              cpu
name                     cpu
cpuid                    0000001f
reg                      00000001

To decode the cpuid :

x1f ==> 0000011111

9	8 7 6 5	4 3	2 1	0
0	0 0 0 0	1 1	1 1	1

LSB_ID    = 00
Chip_ID   = 3
Core_ID   = 3
Strand_ID = 1

x1f(31) => LSB_ID 00 / CHIP_ID 3 / core@3 / cpu@1

This can be confirmed from a prtdiag from the domain :

# prtdiag -v
[...]
==================================== CPUs ====================================

     CPU                 CPU                         Run    L2$    CPU   CPU
LSB   Chip                 ID                         MHz     MB    Impl. Mask
---   ----  ----------------------------------------  ----   ---    ----- ----
00     0      0,   1,   2,   3,   4,   5,   6,   7   2520   5.0        7  144
00     1      8,   9,  10,  11,  12,  13,  14,  15   2520   5.0        7  144
00     2     16,  17,  18,  19,  20,  21,  22,  23   2520   5.0        7  144
00     3     24,  25,  26,  27,  28,  29,  30,  31   2520   5.0        7  144

# psrinfo -vp
The physical processor has 4 cores and 8 virtual processors (24-31)
The core has 2 virtual processors (24 25)
The core has 2 virtual processors (26 27)
The core has 2 virtual processors (28 29)
The core has 2 virtual processors (30 31)
SPARC64-VII (portid 1048 impl 0x7 ver 0x90 clock 2520 MHz)

cpuid cheat sheets :

Relationship between the LSB numbers and the starting processor numbers, in hexadecimal/decimal format (applicable to both SPARC64 VI and SPARC64 VII chips) :

LSB Number	CPU Chip 0	CPU Chip 1	CPU Chip 2	CPU Chip 3
00	00/00	08/08	10/16	18/24
01	20/32	28/40	30/48	38/56
02	40/64	48/72	50/80	58/88
03	60/96	68/104	70/112	78/120
04	80/128	88/136	90/144	98/152
05	a0/160	a8/168	b0/176	b8/184
06	c0/192	c8/200	d0/208	d8/216
07	e0/224	e8/232	f0/240	f8/248
08	100/256	108/264	110/272	118/280
09	120/288	128/296	130/304	138/312
10	140/320	148/328	150/336	158/344
11	160/352	168/360	170/368	178/376
12	180/384	188/392	190/400	198/408
13	1a0/416	1a8/424	1b0/432	1b8/440
14	1c0/448	1c8/456	1d0/464	1d8/472
15	1e0/480	1e8/488	1f0/496	1f8/504

How to map the logical location to the physical location?

At this stage, we know the logical location of the processor : LSB#02.
This LSB can be mapped to any XSB in the platform.
To determine the physical location of the component, a 'showboards -v' for the domain can be collected from the active XSCF.

XSCF> showboards -v -d 0

XSB R DID(LSB) Assignment Pwr Conn Conf Test Fault COD
---- - -------- ----------- ---- ---- ---- ------- -------- ----
00-0 00(00) Assigned y y y Passed Normal n
01-0 00(01) Assigned y y y Passed Normal n
02-0 00(02) Assigned y y y Passed Normal n

From the output, LSB 02 is associated to XSB#02-0.
So, cpuid 82 is pointing to the strand#0 of the core#1 of the chip#2 on the CMU (it's a M9000) in slot 2.

Another example

This reasoning is applicable to the Mid-Range Servers (M4000 + M5000) and High-End Servers (M8000 + M9000); for domain composed of Uni and Quad XSB.

Let's have a look at the same portid/cpuid (x450/x52(82))

{12} ok cd /cmp@450,0/core@1/cpu@0
{12} ok .properties
status okay
device_type cpu
name cpu
cpuid 00000052
reg 00000000

We know from the previous decoding that :

- /cmp@450,0/core@1/cpu@0 ==> ( LSB_ID 02 / CHIP_ID 2 ) / core@1 / cpu@0
- x52(82) => LSB_ID 02 / CHIP_ID 2 / core@1 / cpu@0

prtdiag from the domain confirms that cpuid 82 is the strand#0 of the core#1 of the chip#2 on the LSB#02

==================================== CPUs ==================================== CPU CPU Run L2$ CPU CPU
LSB Chip ID MHz MB Impl. Mask
--- ---- -------------------- ---- --- ----- ----
00 0 0, 1, 2, 3 2280 5.0 6 146
00 1 8, 9, 10, 11 2280 5.0 6 146
00 2 16, 17, 18, 19 2280 5.0 6 146
00 3 24, 25, 26, 27 2280 5.0 6 146
01 3 56, 57, 58, 59 2280 5.0 6 146
02 2 80, 81, 82, 83 2280 5.0 6 146
03 1 104, 105, 106, 107 2280 5.0 6 146
04 0 128, 129, 130, 131 2280 5.0 6 146

But in this example, the physical mapping is as follows :

XSCF> showboards -v -d 1
XSB R DID(LSB) Assignment Pwr Conn Conf Test Fault COD
---- - -------- ----------- ---- ---- ---- ------- -------- ----
08-0 01(00) Assigned y y y Passed Normal n
10-0 01(04) Assigned y y y Passed Normal n
10-1 01(03) Assigned y y y Passed Normal n
10-2 01(02) Assigned y y y Passed Normal n
10-3 01(01) Assigned y y y Passed Normal n

So, in this case, LSB 02 is assigned to a Quad-XSB#10-2.
Therefore cpuid 82 is pointing to the strand#0 of the core#1 of the chip#2 on the CMU (it's a M9000) in slot 10.

Internal Comments

It's possible to obtain details about the CMU/CPUM configuration from the OBP.
In the following example, we are getting
information from the CMU associated with LSB#8 (/CMU#10) :
{100} ok 8 .hwd-cmu

=== HWD LSB#8 CMU ===

4881.f1323210 feba3210 | cmu-comp-name ------------
4881.f1323230 feba3230 | cmu-fru-name ------------- /CMU#10
4881.f1323250 feba3250 | cmu-cmp[0] ---------------
4881.f1323250 feba3250 | | cmp-status ------------- 0000.0004
4881.f1323254 feba3254 | | cmp-comp-name ----------
4881.f1323274 feba3274 | | cmp-fru-name ----------- /CMU#10/CPUM#0
4881.f1323294 feba3294 | | cmp-compatible --------- FJSV,SPARC64-VI
4881.f13232b4 feba32b4 | | cmp-portid ------------- 0500
4881.f13232d0 feba32d0 | | cmp-core[0] (.hwd-co
4881.f13232d0 feba32d0 | | | core-status ---------- 0000.0004
4881.f13232d4 feba32d4 | | | core-comp-name -------
4881.f13232f8 feba32f8 | | | core-frequency ------- 00000000.87e60a00
4881.f1323300 feba3300 | | | core-config ---------- 00000000.00009901
4881.f1323308 feba3308 | | | core-version --------- 00040006.92000507
4881.f1323310 feba3310 | | | core-manu. ----------- 0004
4881.f1323312 feba3312 | | | core-impl. ----------- 0006
4881.f1323314 feba3314 | | | core-mask ------------ 92
4881.f1323318 feba3318 | | | core-l1-i$size ------- 0002.0000
4881.f132331c feba331c | | | core-l1-i$line-size -- 0040
4881.f132331e feba331e | | | core-l1-i$assoc. ----- 0002
4881.f1323320 feba3320 | | | core-#itlb-entries --- 0000.0020
4881.f1323324 feba3324 | | | core-l1-d$size ------- 0002.0000
4881.f1323328 feba3328 | | | core-l1-d$line-size -- 0040
4881.f132332a feba332a | | | core-l1-d$assoc. ----- 0002
4881.f132332c feba332c | | | core-#dtlb-entries --- 0000.0020
4881.f1323340 feba3340 | | | core-l2-$size -------- 0050.0000
4881.f1323344 feba3344 | | | core-l2-$line-size --- 0040
4881.f1323346 feba3346 | | | core-l2-$assoc. ------ 000a
4881.f1323348 feba3348 | | | core-l2-$sharing ----- 0000
4881.f1323360 feba3360 | | | core-strand[0] -------
4881.f1323360 feba3360 | | | | strand-status ------ 0000.0004
4881.f1323364 feba3364 | | | | strand-comp-name ---
4881.f1323384 feba3384 | | | | strand-portid ------ 0100
4881.f13233a0 feba33a0 | | | core-strand[1] -------
4881.f13233a0 feba33a0 | | | | strand-status ------ 0000.0004
4881.f13233a4 feba33a4 | | | | strand-comp-name ---
4881.f13233c4 feba33c4 | | | | strand-portid ------ 0101
4881.f1323470 feba3470 | | cmp-core[1] (.hwd-co
4881.f1323470 feba3470 | | | core-status ---------- 0000.0004
4881.f1323474 feba3474 | | | core-comp-name -------
4881.f1323498 feba3498 | | | core-frequency ------- 00000000.87e60a00
4881.f13234a0 feba34a0 | | | core-config ---------- 00000000.00009902
4881.f13234a8 feba34a8 | | | core-version --------- 00040006.92000507
4881.f13234b0 feba34b0 | | | core-manu. ----------- 0004
4881.f13234b2 feba34b2 | | | core-impl. ----------- 0006
4881.f13234b4 feba34b4 | | | core-mask ------------ 92
4881.f13234b8 feba34b8 | | | core-l1-i$size ------- 0002.0000
4881.f13234bc feba34bc | | | core-l1-i$line-size -- 0040
4881.f13234be feba34be | | | core-l1-i$assoc. ----- 0002
4881.f13234c0 feba34c0 | | | core-#itlb-entries --- 0000.0020
4881.f13234c4 feba34c4 | | | core-l1-d$size ------- 0002.0000
4881.f13234c8 feba34c8 | | | core-l1-d$line-size -- 0040
4881.f13234ca feba34ca | | | core-l1-d$assoc. ----- 0002
4881.f13234cc feba34cc | | | core-#dtlb-entries --- 0000.0020
4881.f13234e0 feba34e0 | | | core-l2-$size -------- 0050.0000
4881.f13234e4 feba34e4 | | | core-l2-$line-size --- 0040
4881.f13234e6 feba34e6 | | | core-l2-$assoc. ------ 000a
4881.f13234e8 feba34e8 | | | core-l2-$sharing ----- 0000
4881.f1323500 feba3500 | | | core-strand[0] -------
4881.f1323500 feba3500 | | | | strand-status ------ 0000.0004
4881.f1323504 feba3504 | | | | strand-comp-name ---
4881.f1323524 feba3524 | | | | strand-portid ------ 0102
4881.f1323540 feba3540 | | | core-strand[1] -------
4881.f1323540 feba3540 | | | | strand-status ------ 0000.0004
4881.f1323544 feba3544 | | | | strand-comp-name ---
4881.f1323564 feba3564 | | | | strand-portid ------ 0103
4881.f1323610 feba3610 | | cmp-core[2] (.hwd-co
4881.f1323610 feba3610 | | | core-status ---------- 0000.0002
4881.f1323614 feba3614 | | | core-comp-name -------
4881.f1323638 feba3638 | | | core-frequency ------- 00000000.00000000
4881.f1323640 feba3640 | | | core-config ---------- 00000000.00000000
4881.f1323648 feba3648 | | | core-version --------- 00000000.00000000
4881.f1323650 feba3650 | | | core-manu. ----------- 0000
4881.f1323652 feba3652 | | | core-impl. ----------- 0000
4881.f1323654 feba3654 | | | core-mask ------------ 00
4881.f1323658 feba3658 | | | core-l1-i$size ------- 0000.0000
4881.f132365c feba365c | | | core-l1-i$line-size -- 0000
4881.f132365e feba365e | | | core-l1-i$assoc. ----- 0000
4881.f1323660 feba3660 | | | core-#itlb-entries --- 0000.0000
4881.f1323664 feba3664 | | | core-l1-d$size ------- 0000.0000
4881.f1323668 feba3668 | | | core-l1-d$line-size -- 0000
4881.f132366a feba366a | | | core-l1-d$assoc. ----- 0000
4881.f132366c feba366c | | | core-#dtlb-entries --- 0000.0000
4881.f1323680 feba3680 | | | core-l2-$size -------- 0000.0000
4881.f1323684 feba3684 | | | core-l2-$line-size --- 0000
4881.f1323686 feba3686 | | | core-l2-$assoc. ------ 0000
4881.f1323688 feba3688 | | | core-l2-$sharing ----- 0000
4881.f13236a0 feba36a0 | | | core-strand[0] -------
4881.f13236a0 feba36a0 | | | | strand-status ------ 0000.0002
4881.f13236a4 feba36a4 | | | | strand-comp-name ---
4881.f13236c4 feba36c4 | | | | strand-portid ------ 0000
4881.f13236e0 feba36e0 | | | core-strand[1] -------
4881.f13236e0 feba36e0 | | | | strand-status ------ 0000.0002
4881.f13236e4 feba36e4 | | | | strand-comp-name ---
4881.f1323704 feba3704 | | | | strand-portid ------ 0000
4881.f13237b0 feba37b0 | | cmp-core[3] (.hwd-co
4881.f13237b0 feba37b0 | | | core-status ---------- 0000.0002
4881.f13237b4 feba37b4 | | | core-comp-name -------
4881.f13237d8 feba37d8 | | | core-frequency ------- 00000000.00000000
4881.f13237e0 feba37e0 | | | core-config ---------- 00000000.00000000
4881.f13237e8 feba37e8 | | | core-version --------- 00000000.00000000
4881.f13237f0 feba37f0 | | | core-manu. ----------- 0000
4881.f13237f2 feba37f2 | | | core-impl. ----------- 0000
4881.f13237f4 feba37f4 | | | core-mask ------------ 00
4881.f13237f8 feba37f8 | | | core-l1-i$size ------- 0000.0000
4881.f13237fc feba37fc | | | core-l1-i$line-size -- 0000
4881.f13237fe feba37fe | | | core-l1-i$assoc. ----- 0000
4881.f1323800 feba3800 | | | core-#itlb-entries --- 0000.0000
4881.f1323804 feba3804 | | | core-l1-d$size ------- 0000.0000
4881.f1323808 feba3808 | | | core-l1-d$line-size -- 0000
4881.f132380a feba380a | | | core-l1-d$assoc. ----- 0000
4881.f132380c feba380c | | | core-#dtlb-entries --- 0000.0000
4881.f1323820 feba3820 | | | core-l2-$size -------- 0000.0000
4881.f1323824 feba3824 | | | core-l2-$line-size --- 0000
4881.f1323826 feba3826 | | | core-l2-$assoc. ------ 0000
4881.f1323828 feba3828 | | | core-l2-$sharing ----- 0000
4881.f1323840 feba3840 | | | core-strand[0] -------
4881.f1323840 feba3840 | | | | strand-status ------ 0000.0002
4881.f1323844 feba3844 | | | | strand-comp-name ---
4881.f1323864 feba3864 | | | | strand-portid ------ 0000
4881.f1323880 feba3880 | | | core-strand[1] -------
4881.f1323880 feba3880 | | | | strand-status ------ 0000.0002
4881.f1323884 feba3884 | | | | strand-comp-name ---
4881.f13238a4 feba38a4 | | | | strand-portid ------ 0000
4881.f1323960 feba3960 | cmu-cmp[1] ---------------
4881.f1323960 feba3960 | | cmp-status ------------- 0000.0004
4881.f1323964 feba3964 | | cmp-comp-name ----------
4881.f1323984 feba3984 | | cmp-fru-name ----------- /CMU#10/CPUM#1
4881.f13239a4 feba39a4 | | cmp-compatible --------- FJSV,SPARC64-VI
4881.f13239c4 feba39c4 | | cmp-portid ------------- 0508
[...]

For SPARC64 VII :

{e} ok 0 .hwd-cmu

=== HWD LSB#0 CMU ===
4081.f1323210 fefa3210 | cmu-comp-name ------------
4081.f1323230 fefa3230 | cmu-fru-name ------------- /CMU#0
4081.f1323250 fefa3250 | cmu-cmp[0] ---------------
4081.f1323250 fefa3250 | | cmp-status ------------- 0000.0004
4081.f1323254 fefa3254 | | cmp-comp-name ----------
4081.f1323274 fefa3274 | | cmp-fru-name ----------- /CMU#0/CPUM#0
4081.f1323294 fefa3294 | | cmp-compatible --------- FJSV,SPARC64-VII
4081.f13232b4 fefa32b4 | | cmp-portid ------------- 0400
4081.f13232d0 fefa32d0 | | cmp-core[0] (.hwd-co
4081.f13232d0 fefa32d0 | | | core-status ---------- 0000.0004
4081.f13232d4 fefa32d4 | | | core-comp-name -------
4081.f13232f8 fefa32f8 | | | core-frequency ------- 00000000.96342600
4081.f1323300 fefa3300 | | | core-config ---------- 00000000.0000a801
4081.f1323308 fefa3308 | | | core-version --------- 00040007.90000507
4081.f1323310 fefa3310 | | | core-manu. ----------- 0004
4081.f1323312 fefa3312 | | | core-impl. ----------- 0007
4081.f1323314 fefa3314 | | | core-mask ------------ 90
4081.f1323318 fefa3318 | | | core-l1-i$size ------- 0001.0000
4081.f132331c fefa331c | | | core-l1-i$line-size -- 0040
4081.f132331e fefa331e | | | core-l1-i$assoc. ----- 0002
4081.f1323320 fefa3320 | | | core-#itlb-entries --- 0000.0020
4081.f1323324 fefa3324 | | | core-l1-d$size ------- 0001.0000
4081.f1323328 fefa3328 | | | core-l1-d$line-size -- 0040
4081.f132332a fefa332a | | | core-l1-d$assoc. ----- 0002
4081.f132332c fefa332c | | | core-#dtlb-entries --- 0000.0020
4081.f1323340 fefa3340 | | | core-l2-$size -------- 0050.0000
4081.f1323344 fefa3344 | | | core-l2-$line-size --- 0100
4081.f1323346 fefa3346 | | | core-l2-$assoc. ------ 000a
4081.f1323348 fefa3348 | | | core-l2-$sharing ----- 0000
4081.f1323360 fefa3360 | | | core-strand[0] -------
4081.f1323360 fefa3360 | | | | strand-status ------ 0000.0004
4081.f1323364 fefa3364 | | | | strand-comp-name ---
4081.f1323384 fefa3384 | | | | strand-portid ------ 0000
4081.f13233a0 fefa33a0 | | | core-strand[1] -------
4081.f13233a0 fefa33a0 | | | | strand-status ------ 0000.0004
4081.f13233a4 fefa33a4 | | | | strand-comp-name ---
4081.f13233c4 fefa33c4 | | | | strand-portid ------ 0001
4081.f1323470 fefa3470 | | cmp-core[1] (.hwd-co
4081.f1323470 fefa3470 | | | core-status ---------- 0000.0004
4081.f1323474 fefa3474 | | | core-comp-name -------
4081.f1323498 fefa3498 | | | core-frequency ------- 00000000.96342600
4081.f13234a0 fefa34a0 | | | core-config ---------- 00000000.0000a802
4081.f13234a8 fefa34a8 | | | core-version --------- 00040007.90000507
4081.f13234b0 fefa34b0 | | | core-manu. ----------- 0004
4081.f13234b2 fefa34b2 | | | core-impl. ----------- 0007
4081.f13234b4 fefa34b4 | | | core-mask ------------ 90
4081.f13234b8 fefa34b8 | | | core-l1-i$size ------- 0001.0000
4081.f13234bc fefa34bc | | | core-l1-i$line-size -- 0040
4081.f13234be fefa34be | | | core-l1-i$assoc. ----- 0002
4081.f13234c0 fefa34c0 | | | core-#itlb-entries --- 0000.0020
4081.f13234c4 fefa34c4 | | | core-l1-d$size ------- 0001.0000
4081.f13234c8 fefa34c8 | | | core-l1-d$line-size -- 0040
4081.f13234ca fefa34ca | | | core-l1-d$assoc. ----- 0002
4081.f13234cc fefa34cc | | | core-#dtlb-entries --- 0000.0020
4081.f13234e0 fefa34e0 | | | core-l2-$size -------- 0050.0000
4081.f13234e4 fefa34e4 | | | core-l2-$line-size --- 0100
4081.f13234e6 fefa34e6 | | | core-l2-$assoc. ------ 000a
4081.f13234e8 fefa34e8 | | | core-l2-$sharing ----- 0000
4081.f1323500 fefa3500 | | | core-strand[0] -------
4081.f1323500 fefa3500 | | | | strand-status ------ 0000.0004
4081.f1323504 fefa3504 | | | | strand-comp-name ---
4081.f1323524 fefa3524 | | | | strand-portid ------ 0002
4081.f1323540 fefa3540 | | | core-strand[1] -------
4081.f1323540 fefa3540 | | | | strand-status ------ 0000.0004
4081.f1323544 fefa3544 | | | | strand-comp-name ---
4081.f1323564 fefa3564 | | | | strand-portid ------ 0003
4081.f1323610 fefa3610 | | cmp-core[2] (.hwd-co
4081.f1323610 fefa3610 | | | core-status ---------- 0000.0004
4081.f1323614 fefa3614 | | | core-comp-name -------
4081.f1323638 fefa3638 | | | core-frequency ------- 00000000.96342600
4081.f1323640 fefa3640 | | | core-config ---------- 00000000.0000a804
4081.f1323648 fefa3648 | | | core-version --------- 00040007.90000507
4081.f1323650 fefa3650 | | | core-manu. ----------- 0004
4081.f1323652 fefa3652 | | | core-impl. ----------- 0007
4081.f1323654 fefa3654 | | | core-mask ------------ 90
4081.f1323658 fefa3658 | | | core-l1-i$size ------- 0001.0000
4081.f132365c fefa365c | | | core-l1-i$line-size -- 0040
4081.f132365e fefa365e | | | core-l1-i$assoc. ----- 0002
4081.f1323660 fefa3660 | | | core-#itlb-entries --- 0000.0020
4081.f1323664 fefa3664 | | | core-l1-d$size ------- 0001.0000
4081.f1323668 fefa3668 | | | core-l1-d$line-size -- 0040
4081.f132366a fefa366a | | | core-l1-d$assoc. ----- 0002
4081.f132366c fefa366c | | | core-#dtlb-entries --- 0000.0020
4081.f1323680 fefa3680 | | | core-l2-$size -------- 0050.0000
4081.f1323684 fefa3684 | | | core-l2-$line-size --- 0100
4081.f1323686 fefa3686 | | | core-l2-$assoc. ------ 000a
4081.f1323688 fefa3688 | | | core-l2-$sharing ----- 0000
4081.f13236a0 fefa36a0 | | | core-strand[0] -------
4081.f13236a0 fefa36a0 | | | | strand-status ------ 0000.0004
4081.f13236a4 fefa36a4 | | | | strand-comp-name ---
4081.f13236c4 fefa36c4 | | | | strand-portid ------ 0004
4081.f13236e0 fefa36e0 | | | core-strand[1] -------
4081.f13236e0 fefa36e0 | | | | strand-status ------ 0000.0004
4081.f13236e4 fefa36e4 | | | | strand-comp-name ---
4081.f1323704 fefa3704 | | | | strand-portid ------ 0005
4081.f13237b0 fefa37b0 | | cmp-core[3] (.hwd-co
4081.f13237b0 fefa37b0 | | | core-status ---------- 0000.0004
4081.f13237b4 fefa37b4 | | | core-comp-name -------
4081.f13237d8 fefa37d8 | | | core-frequency ------- 00000000.96342600
4081.f13237e0 fefa37e0 | | | core-config ---------- 00000000.0000a806
4081.f13237e8 fefa37e8 | | | core-version --------- 00040007.90000507
4081.f13237f0 fefa37f0 | | | core-manu. ----------- 0004
4081.f13237f2 fefa37f2 | | | core-impl. ----------- 0007
4081.f13237f4 fefa37f4 | | | core-mask ------------ 90
4081.f13237f8 fefa37f8 | | | core-l1-i$size ------- 0001.0000
4081.f13237fc fefa37fc | | | core-l1-i$line-size -- 0040
4081.f13237fe fefa37fe | | | core-l1-i$assoc. ----- 0002
4081.f1323800 fefa3800 | | | core-#itlb-entries --- 0000.0020
4081.f1323804 fefa3804 | | | core-l1-d$size ------- 0001.0000
4081.f1323808 fefa3808 | | | core-l1-d$line-size -- 0040
4081.f132380a fefa380a | | | core-l1-d$assoc. ----- 0002
4081.f132380c fefa380c | | | core-#dtlb-entries --- 0000.0020
4081.f1323820 fefa3820 | | | core-l2-$size -------- 0050.0000
4081.f1323824 fefa3824 | | | core-l2-$line-size --- 0100
4081.f1323826 fefa3826 | | | core-l2-$assoc. ------ 000a
4081.f1323828 fefa3828 | | | core-l2-$sharing ----- 0000
4081.f1323840 fefa3840 | | | core-strand[0] -------
4081.f1323840 fefa3840 | | | | strand-status ------ 0000.0004
4081.f1323844 fefa3844 | | | | strand-comp-name ---
4081.f1323864 fefa3864 | | | | strand-portid ------ 0006
4081.f1323880 fefa3880 | | | core-strand[1] -------
4081.f1323880 fefa3880 | | | | strand-status ------ 0000.0004
4081.f1323884 fefa3884 | | | | strand-comp-name ---
4081.f13238a4 fefa38a4 | | | | strand-portid ------ 0007
4081.f1323960 fefa3960 | cmu-cmp[1] ---------------
4081.f1323960 fefa3960 | | cmp-status ------------- 0000.0004
4081.f1323964 fefa3964 | | cmp-comp-name ----------
4081.f1323984 fefa3984 | | cmp-fru-name ----------- /CMU#0/CPUM#1
4081.f13239a4 fefa39a4 | | cmp-compatible --------- FJSV,SPARC64-VII
[...]

References

<NOTE:1011446.1> - Sun SPARC� Enterprise Mx000 Servers : Logical System Board (LSB)
"Sun SPARC Enterprise M3000/M4000/M5000/M8000/M9000 Servers Administration Guide" - Appendix A - Mapping Device Path Names

Attachments

This solution has no attachment