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Asset ID: 1-73-1000843.1
Update Date:2010-11-10
Keywords:

Solution Type  FAB (standard) Sure

Solution  1000843.1 :   V490 XOption Upgrade's causing outages due to down rev OBP  


Related Items
  • Sun Fire V490 Server
  •  
Related Categories
  • GCS>Sun Microsystems>Sun FAB>Standard>Controlled Proactive
  •  

PreviouslyPublishedAs
201124


Product
Sun Fire V490 Server


Symptoms

Panther based Customers who are installing Panther based CPU Xoptions, X7272A and X7274A, into Sun fire V490 systems are not consistently upgrading OBP to the required version, 4.18.2., due to unconsolidated upgrade instructions.  

This results in CPU errors being reported on Sun Fire V490 Panther based systems.  

Additionally, Solution Centers are not consistently advising customers of the need to upgrade OBP due to unconsolidated upgrade instructions.

Note prtdiag output below: 

| <*>                                                                          |
| Hardware Power On                                                            |
| @(#)OBP 4.15.6 2005/05/09 06:18 Sun Fire 4XX                                 |
| Front Panel Keyswitch is in Diagnostic position.                             |
| System is initializing in Service Mode.                                      |
| Online: CPU0 CPU2*                                                           |
| Validating JTAG integrity...Done                                             |
| Disabling DAR error circuitry...Done                                         |
| Clearing DCS error circuitry state...Done                                    |
| Initializing DTL circuitry state...Done                                      |
| Initializing CDX via JTAG...Done                                             |
| Enabling DAR error circuitry...Done                                          |
| Probing core system FRUs..                                                   |
| Probing Centerplane....part# 501-6911-03 serial# 013491                      |
|   Safari min 150MHz, cumulative 150MHz;  max 150MHz, cumulative 150MHz       |
|   'STICK' clock 10MHz; BootBus timing 014f.99fd.a7e6.3f29                    |
| Probing I/O Riser......part# 501-5820-04 serial# 088679                      |
| Probing System RSC.....part# 501-5856-06 serial# 087652                      |
| Probing PwrDistBoard...part# 375-3168-03 serial# O26073                      |
| Probing PowerSupply0...part# 300-1632-06 serial# P15555                      |
| Probing PowerSupply1...part# 300-1632-056serial# P17369                      |
| Probing FCAL BPlane0...part# 501-5822-04 serial# 087847                      |
| Probing GPTwo Slot A...part# 501-7058-01 serial# 007369                      |
|   Safari min 150MHz, cumulative 150MHz;  max 150MHz, cumulative 150MHz       |
|   CPU rated speed 1500MHz; ECache 8MB 3.3ns                                  |
| Probing GPTwo Slot B...No module detected Done                               |
| Desired Safari Bus speed 150MHz, selecting 150MHz                            |
| Configuring CPUs..........                                                   |
| ... CPU0 Rated Speed 1500MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU       |
| 1500MHz                                                                      |
|          Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00         |
| ... CPU2 Rated Speed 1500MHz, Safari 150MHz, want 8:1, got 8:1 ==> CPU       |
| 1500MHz                                                                      |
|          Ecache 8MB 3.3ns mode=5-4-4 2-way ECCR: 0000.0000.0343.4c00 Done    |
| Setting system speed (and resetting)...                                      |
| <*>                                                                          |
| Set Speed Reset                                                              |
| @(#)OBP 4.15.6 2005/05/09 06:18 Sun Fire 4XX                                 |
| Front Panel Keyswitch is in Diagnostic position.                             |
| System is initializing in Service Mode.                                      |
| Online: *CPU2 UltraSPARC IV(v2.4) 8:1 1500MHz 8MB 4:1 ECache                 |
| Executing POST w/%o0 = 0000.1000.0101.4043                                   |
| 2:0>2                                                                        |
| 2:0>@(#) Sun Fire[TM] V480/V490 POST 4.15.6 2005/05/09 06:18                 |
|        /dat/fw/common-source/firmware_re/post/post-build-                    |
| 4.15.6/Camelot/cstone/i                                                      |
| ntegrated  (firmware_re)                                                     |
| 2:0>Copyright ? 2005 Sun Microsystems, Inc. All rights reserved              |
|   SUN PROPRIETARY/CONFIDENTIAL.                                              |
|   Use is subject to license terms.                                           |
| 2:0>Jump from OBP->POST.                                                     |
| 2:0>diag-switch? configuration variable set TRUE.                            |
| 2:0>Keyswitch in DIAGNOSTIC POSITION.                                        |
| 2:0>Diag level set to MAX.                                                   |
| 2:0>Verbosity level set to MAX.                                              |
| 2:0>MFG scrpt mode set NORM                                                  |
| 2:0>I/O port set to serial TTYA.                                             |
| 2:0>                                                                         |
| 2:0>Start selftest...                                                        |
| 2:0>CPUs present in system: 2:0                                              |
| 2:0>Test CPU(s).....                                                         |
| 2:0>Init CPU                                                                 |
| 2:0>    UltraSparc_IV_plus Version 2.4                                       |
| 2:0>DMMU Registers Access                                                    |
| 2:0>DMMU TLB DATA RAM Access                                                 |
| 2:0>DMMU TLB TAGS Access                                                     |
| 2:0>IMMU Registers Access                                                    |
| 2:0>IMMU TLB DATA RAM Access                                                 |
| 2:0>IMMU TLB TAGS Access                                                     |
| 2:0>Probe Ecache                                                             |
| 2:0>    Size = 00000000.00800000...                                          |
| 2:0>Ecache Data Bitwalk                                                      |
| 2:0>Ecache Address Bitwalk                                                   |
| 2:0>Scrub and Setup Ecache                                                   |
| 2:0>Setup and Enable DMMU                                                    |
| 2:0>Setup DMMU Miss Handler                                                  |
| 2:0>Test and Init Temp Mailbox                                               |
| 2:0>                                                                         |
| 2:0>ERROR: TEST = Check cpu synch var CPU 0                                  |
| 2:0>H/W under test = CPU0 Basic, Motherboard/Centerplane                     |
| 2:0>Repair Instructions: Replace items in order listed by 'H/W under test'   |
| above                                                                        |
| .                                                                            |
| 2:0>MSG = CPU 0:0 failed BBC SRAM access, offline cpu.                       |
| 2:0>END_ERROR                                                                |
| 2:0>                                                                         |
| 2:0>ERROR: TEST = Check cpu synch var CPU 0                                  |
| 2:0>H/W under test = CPU0 Basic, Motherboard/Centerplane                     |
| 2:0>Repair Instructions: Replace items in order listed by 'H/W under test'   |
| above                                                                        |
| .                                                                            |
| 2:0>MSG =                                                                    |
|          *** Test Failed!! ***                                               |
| 2:0>END_ERROR                                                                |
| 2:0>                                                                         |
| 2:0>ERROR: TEST = Check cpu synch var CPU 0                                  |
| 2:0>H/W under test = CPU0 Basic, Motherboard/Centerplane                     |
| 2:0>Repair Instructions: Replace items in order listed by 'H/W under test'   |
| above                                                                        |
| .                                                                            |
| 2:0>MSG = ERROR:        Fatal CPU error on master, rolling over to new       |
| master.                                                                      |
| 2:0>END_ERROR                                                                |
| 2:0>Soft Reset.                                                              |
| 2:0>                                                                         |
| 2:0>ERROR: TEST = Power on Reset Initialization                              |
| 2:0>H/W under test = CPU2 Basic, Motherboard/Centerplane                     |
| 2:0>Repair Instructions: Replace items in order listed by 'H/W under test'   |
| above                                                                        |
| .                                                                            |
| 2:0>MSG = Watchdog timeout, Master CPU Failure on 2:0, rollover to 2:0.      |
| 2:0>END_ERROR                                                                |
| 2:0>ERROR:      No good CPUs left!  Calling debug menu.                      |
| 2:0>    0       Peek/Poke interface                                          |
| 2:0>    1       Dump DAR Error Bits                                          |
| 2:0>    2       Dump Scan Chain                                              |
| 2:0>    3       Dump CPU Regs                                                |
| 2:0>    4       Dump BBC Regs                                                |
| 2:0>    5       Dump Mem Controller Regs                                     |
| 2:0>    6       Dump Valid DMMU entries                                      |
| 2:0>    7       Dump IMMU entries                                            |
| 2:0>    8       Dump Struct Info                                             |
| 2:0>    9       Dump Mailbox                                                 |
| 2:0>    a       Dump IO-Bridge regs unit 0                                   |
| 2:0>    b       Dump IO-Bridge regs unit 1                                   |
| 2:0>    c       Allow other CPUs to print                                    |
| 2:0>    d       Do soft reset                                                |
| 2:0>    ?       Help                                                         |
| 2:0>                                                                         |
| 2:0>Selection:                                                               |
================================================================================


Workaround

Services Call centers to check OBP versions before dispatching replacement Panther CPU modules. Advise customers availability of required patch 119242-01


Resolution

Product team to improve the Installation Document which accompanies all new Panther CPU X options.


Previously Published As
102036
Internal Comments


Internal Eng Business Unit Group
KE Authors

Internal Kasp FAB Legacy ID
102036

Internal Sun Alert & FAB Admin Info
Critical Category:
Significant Change Date:
Avoidance:
Responsible Manager: null
Original Admin Info: null

Product_uuid
5c71fc02-5e51-11d7-8add-8938754df22a|Sun Fire V490 Server

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